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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9740 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 10-bit, 165 msps txdac d/a converter functional block diagram 150pf +1.20v ref avdd acom reflo current source array 3.3v segmented switches lsb switch refio fs adj dvdd dcom clock 3.3v r set 0.1 f clock iouta ioutb latches ad9740 sleep digital data inputs (db9db0) mode features high-performance member of pin-compatible txdac product family excellent spurious-free dynamic range performance snr @ 5 mhz output, 125 msps: 65 db twos complement or straight binary data format differential current outputs: 2 ma to 20 ma power dissipation: 135 mw @ 3.3 v power-down mode: 15 mw @ 3.3 v on-chip 1.20 v reference cmos-compatible digital interface package: 28-lead soic and tssop packages edge-triggered latches applications wideband communication transmit channel: direct if base stations wireless local loop digital radio link direct digital synthesis (dds) instrumentation product description the ad9740 is a 10-bit resolution, wideband, third generation member of the txdac series of high-performance, low power cmos digital-to-analog converters (dacs). the txdac family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit dacs, is specifically optimized for the transmit signal path of communica- tion systems. all of the devices share the same interface options, small outline package, and pinout, providing an upward or down- ward component selection path based on performance, resolution, and cost. the ad9740 offers exceptional ac and dc performance while supporting update rates up to 165 msps. the ad9740? low power dissipation makes it well suited for portable and low power applications. its power dissipation can be further reduced to a mere 60 mw with a slight degradation in performance by lowering the full-scale current output. also, a power-down mode reduces the standby power dissipation to approximately 15 mw. a segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. edge- triggered input latches and a 1.2 v temperature compensated band gap reference have been integrated to provide a complete monolithic dac solution. the digital inputs support 3 v cmos logic families. product highlights 1. the ad9740 is the 10-bit member of the pin-compatible txdac family that offers excellent inl and dnl performance. 2. data input supports two? complement or straight binary data coding. 3. high-speed, single-ended cmos clock input supports 165 msps conversion rate. 4. low power: complete cmos dac function operates on 135 mw from a 3.0 v to 3.6 v single supply. the dac full- scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. on-chip voltage reference: the ad9740 includes a 1.2 v temperature-compensated band gap voltage reference. 6. industry standard 28-lead soic and tssop packages. txdac is a registered trademark of analog devices, inc. * protected by u.s. patent numbers 5568145, 5689257, and 5703519.
rev. 0 ?2? ad9740 dc specifications parameter min typ max unit resolution 10 bits dc accuracy 1 integral linearity error (inl) e0.7 () () () ? () ? () () ( ) ( ) ( ) = = = ? = = ( == =)
rev. 0 ?3? ad9740 dynamic specifications parameter min typ max unit dynamic performance maximum output update rate (f clock ) 165 msps output settling time (t st ) (to 0.1%) 1 11 ns output propagation delay (t pd )1ns glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (10% to 90%) 1 2.5 ns output noise (i outfs = 20 ma) 2 50 pa/ hz hz hz hz hz hz hz hz hz hz hz hzhz hzhz hzhz hzhz h hz hz hz hz hz hz hz hz hz hz hz hzhz ? ( == = )
rev. 0 ?4? ad9740 ordering guide temperature package package model range description options * ad9740ar e40 == ja = 71.4 ja = 97.9 () () ( ) ( ) ( ) ( == =)
rev. 0 ad9740 ?5? pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad9740 nc = no connect (msb) db9 db8 db7 db6 db5 db4 db3 db2 (lsb) db0 nc nc nc nc clock dvdd dcom mode avdd reserved iouta ioutb acom nc fs adj refio reflo sleep db1 pin function descriptions pin no. mnemonic description 1 db9 most significant data bit (msb) 2e9 db8edb1 data bits 8e1 10 db0 least significant data bit (lsb) 11e14 nc no internal connection 15 sleep power-down control input. active high. contains active pull-down circuit; it may be left unterminated if not used. 16 reflo reference ground when internal 1.2 v reference used. connect to avdd to disable internal reference. 17 refio ref erence input/output. serves as reference input when internal reference disabled (i.e., tie reflo to avdd). serves as 1.2 v reference output when internal reference activated (i.e., tie reflo to agnd). requ ires 0.1 () ()
rev. 0 ad9740 ?6? definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called the offset error. for iouta, 0 ma output is expected when the inputs are all 0s. for ioutb, 0 ma output is ex pected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25 ) () () ?
rev. 0 ?7? t ypical performance characteristicsead9740 f out e mhz sfdr e dbc 45 110 100 65msps 125msps 165msps 50 55 60 65 70 75 80 85 90 95 tpc 1. sfdr vs. f out @ 0 dbfs 060 10 45 50 55 60 65 70 75 80 85 90 95 f out e mhz sfdr e dbc 40 30 20 50 e12dbfs e6dbfs 0dbfs tpc 4. sfdr vs. f out @ 165 msps e20 e15 e25 e10 e5 0 45 55 65 75 85 95 a out e mhz sfdr e dbc 165msps 125msps 65msps tpc 7. single-tone sfdr vs. a out @ f out = f clock /5 05 25 10 15 20 45 50 55 60 65 70 75 80 85 90 95 f out e mhz sfdr e dbc e12dbfs e6dbfs 0dbfs tpc 2. sfdr vs. f out @ 65 msps 05 25 10 15 20 45 50 55 60 65 70 75 80 85 90 95 20ma 10ma 5ma f out e mhz sfdr e dbc tpc 5. sfdr vs. f out and i outfs @ 65 msps and 0 dbfs 90 110 70 130 150 170 60 65 70 75 85 90 20ma f clock e msps snr e db 10ma 5ma 50 80 tpc 8. snr vs. f clock and i outfs @ f out = 5 mhz and 0 dbfs 05 45 10 15 35 45 50 55 60 65 70 75 80 85 90 95 0dbfs e6dbfs e12dbfs f out e mhz sfdr e dbc 40 30 20 25 tpc 3. sfdr vs. f out @ 125 msps 0 e5 e25 e10 e15 e20 45 55 65 75 85 95 a out e dbfs sfdr e dbc 165msps 125msps 65msps tpc 6. single-tone sfdr vs. a out @ f out = f clock /11 45 50 55 60 65 70 75 80 85 90 95 a out e dbfs sfdr e dbc 0 e5 e10 e15 e20 e25 78msps 165msps 125msps 65msps tpc 9. dual-tone imd vs. a out @ f out = f clock /7
rev. 0 ad9740 ?8? e40 e20 60 02040 50 55 60 65 70 75 80 85 90 4mhz 19mhz 34mhz temperature e c sfdr e dbc 80 49mhz tpc 12. sfdr vs. temperature @ 165 msps, 0 dbfs 16 26 11 16 21 e100 frequency e mhz magnitude e dbm 31 f clock = 78msps f out1 = 15.0mhz f out2 = 15.4mhz f out3 = 15.8mhz f out4 = 16.2mhz sfdr = 72dbc amplitude = 0dbfs 36 e90 e80 e70 e60 e50 e40 e20 0 e10 e30 tpc 15. four-tone sfdr 0 256 512 768 1024 e0.25 e0.15 e0.05 0.05 0.15 0.25 code error e lsb tpc 10. typical inl 16 26 11 16 21 e100 frequency e mhz magnitude e dbm 31 f clock = 78msps f out = 15.0mhz sfdr = 77dbc amplitude = 0dbfs 36 e90 e80 e70 e60 e50 e40 e20 0 e10 e30 tpc 13. single-tone sfdr 0 256 512 768 1024 e0.25 e0.15 e0.05 0.05 0.15 0.25 code error e lsb tpc 11. typical dnl 16 26 11 16 21 e100 frequency e mhz magnitude e dbm 31 f clock = 78msps f out1 = 15.0mhz f out2 = 15.4mhz sfdr = 77dbc amplitude = 0dbfs 36 e90 e80 e70 e60 e50 e40 e20 0 e10 e30 tpc 14. dual-tone sfdr
rev. 0 ad9740 ?9? functional description figure 3 shows a simplified block diagram of the ad9740. the ad9740 consists of a dac, digital control logic, and full-scale output current control. the dac contains a pmos current source array capable of providing up to 20 ma of full-scale current (i outfs ). the array is divided into 31 equal currents that make up the 5 most significant bits (msbs). the next 4 bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an msb current source. the remaining lsbs are binary weighted fractions of the middle bits current sources. implementing the middle and lower bits w ith current sources, instead of an r-2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the dac?s high output impedance (i.e., >100 k ? ) () () () ? ? = () ? =
rev. 0 ad9740 ?10? reference control amplifier the ad9740 contains a control amplifier that is used to regu- late the full-scale output current, i outfs . the control amplifier is configured as a v-i converter as shown in figure 4, so that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied to the segmented current sources with the proper scale factor to set i outfs as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting i ref between 62.5 () ( =) iouta and ioutb is a function of both the input code and i outfs and can be expressed as: iouta dac code i outfs = () () ioutb dac code i outfs = ( ) () dac code = 0 to 1023 (i.e., decimal representation). as mentioned previously, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage, v refio , and external resistor, r set . it can be expressed as: ii outfs ref = () iv r ref refio set = () ? ? iouta and ioutb nodes is simply: v iouta r outa load = () v ioutb r outb load = () v outa and v outb should not exceed the specified output compliance range to maintain specified distortion and linearity performance. v iouta ioutb r diff load = () () iouta , ioutb , i ref , and v diff can be expressed as: v dac code rrv diff load set refio = {} () () () ( ) ( )( ) () ? ( )
rev. 0 ad9740 ?11? iouta and ioutb also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. the negative output compliance range of e1.0 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the ad9740. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.2 v for an i outfs = 20 ma to 1.0 v for an i outfs = 2 ma. the optimum distortion performance for a single-ended or differ- ential output is achieved when the maximum full-scale signal at iouta and ioutb does not exceed 0.5 v. digital inputs the ad9740?s digital section consists of 10 input bit channels and a clock input. the 10-bit parallel data inputs follow stan- dard positive binary coding where db13 is the most significant bit (msb) and db0 is the least significant bit (lsb). iouta produces a full-scale output current when all data bits are at logic 1. ioutb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. dvdd digital input figure 6. equivalent digital input the digital interface is implemented using an edge-triggered master/slave latch. the dac output updates on the rising edge of the clock and is designed to support a clock rate as high as 165 msps. the clock can be operated at any duty cycle that meets the specified latch pulsewidth. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges ma y affect digital feedthrough and distortion performance. best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. dac timing input clock and data timing relationship dynamic performance in a dac is dependent on the relation- ship between the position of the clock edges and the point in time at which the input data changes. the ad9740 is rising edge triggered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. in general, the goal when applying the ad9740 is to make the data transition close to the falling clock edge. this becomes more important as the sample rate increases. figure 7 shows the relationship of sfdr to clock placement with different sample rates. note that at the lower sample rates, more tolerance is allowed in clock place- ment, while at higher rates, more care must be taken. e3 e2 2 e1 0 1 70 80 time (ns) of data change relative to rising clock edge sfdr e dbc 3 60 50 40 65 75 55 45 f out = 50mhz f out = 20mhz figure 7. sfdr vs. clock placement @ f out = 20 mhz and 50 mhz sleep mode operation the ad9740 has a power-down function that turns off the output current and reduces the supply current to less than 4 ma over the specified supply range of 3.0 v to 3.6 v and temperature range. this mode can be activated by applying a logic level 1 to the sleep pin. the sleep pin logic threshold is equal to 0.5 () ( ) =
rev. 0 ad9740 ?12? i outfs e ma 35 0 2 i av d d e ma 30 25 20 15 10 46810 12 14 16 18 20 figure 8. i avdd vs. i outfs ratio e f out / f clock 16 0.01 1 0.1 i dvdd e ma 14 12 10 8 6 4 2 0 165msps 125msps 65msps figure 9. i dvdd vs. ratio @ dvdd = 3.3 v applying the ad9740 output configurations the following sections illustrate some typical output configurations for the ad9740. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requiring the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration may consist of either an rf transformer or a differential op amp configuration. the transformer configuration provides the optimum high-frequency performance and is recommended for any application that allows ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting, within the bandwidth of the chosen op amp. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if iouta and/or ioutb is connected to an appropriately sized load resistor, r load , referred to acom . this configuration may be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. alternatively, an amplifier could be configured as an i-v converter, thus converting iouta or ioutb into a negative unipolar voltage. this configuration provides the best dc linearity since iouta or ioutb is maintained at a virtual ground. differential coupling using a transformer an rf transformer can be used to perform a differential-to-single- ended signal conversion as shown in figure 10. a differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer?s pass band. an rf transformer, such as the mini- circuits t1e1t, provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. transformers with different impedance ratios may also be used for impedance matching pur poses. note that the transformer provides ac coupling only. r load ad9740 mini-circuits t1e1t optional r diff iouta ioutb figure 10. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both iouta and ioutb. the complementary voltages appearing at iouta and ioutb (i.e., v outa and v outb ) swing symmetri- cally around acom and should be maintained with the specified output compliance range of the ad9740. a differential resistor, r diff , may be inserted in applications where the output of the transformer is connected to the load, r load , via a passive recon- struction filter or cable. r diff is determined by the transformer?s impedance ratio and provides the proper source termination that results in a low vswr. note that approximately half the signal power will be dissipated across r diff . differential coupling using an op amp an op amp can also be used to perform a differential-to-single-ended conversion as shown in figure 11. the ad9740 is configured with two equal load resistors, r load , of 25 ?
rev. 0 ad9740 ?13? ad9740 while meeting other system level objectives (i.e., cost, power) should be selected. the op amp?s differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. the differential circuit shown in figure 12 provides the necessary level shifting required in a single-supply system. in this case, avdd, which is the positive analog supply for both the ad9740 and the op amp, is also used to level shift the differential output of the ad9740 to midsupply (i.e., avdd/2). the ad8041 is a suitable op amp for this application. ad9740 iouta ioutb c opt 500 225 225 1k 25 25 ad8041 1k avdd figure 12. single-supply dc differential coupled circuit single-ended unbuffered voltage output figure 13 shows the ad9740 configured to provide a unipolar output range of approximately 0 v to 0.5 v for a doubly termi- nated 50 ? ? () () = = () = = ( )
rev. 0 ad9740 ?14? full-scale current is directed toward that output. as a result, the psrr measurement in figure 15 represents a worst-case condition in which the digital inputs remain static and the full-scale output current of 20 ma is directed to the dac output being measured. an example serves to illustrate the effect of supply noise on the analog supply. suppose a switching regulator with a switching frequency of 250 khz produces 10 mv of noise and, for simplicity sake (i.e., ignore harmonics), all of this noise is concentrated at 250 khz. to calculate how much of this undesired noise will appear as current noise superimposed on the dac?s full-scale current, i outfs , one must determine the psrr in db using fi g ure 15 at 250 khz. to calculate the psrr for a given r load , such that the units of psrr are converted from a/v to v/v, adjust the curve in figure 15 by the scaling factor 20 ( ) ? ( ) ? ? ? ?
rev. 0 ad9740 ?15? 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp5 50 1 rcom 16 1 rp3 22 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db13x db12x db11x db10x db9x db8x db7x db6x db5x db4x db3x db2x db1x db0x 15 2 rp3 22 14 3 rp3 22 13 4 rp3 22 12 5 rp3 22 11 6 rp3 22 10 7 rp3 22 9 8 rp3 22 16 1 rp4 22 15 2 rp4 22 14 3 rp4 22 13 4 rp4 22 12 5 rp4 22 11 6 rp4 22 9 8 rp4 22 10 7 rp4 22 ckext ckextx 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp6 50 1 rcom 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp1 50 1 rcom 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp2 50 1 rcom 21 db13x 4 3 db12x 65 db11x 87 db10x 10 9 db9x 12 11 db8x 14 13 db7x 16 15 db6x 18 17 db5x 20 19 db4x 22 21 db3x 24 23 db2x 26 25 db1x 28 27 db0x 30 29 32 31 34 33 ckextx 36 35 38 37 40 39 jp3 j1 ribbon tb1 1 tb1 2 l2 10 h c7 0.1 f tp4 blk + dvdd tp7 c6 0.1 f c4 10 f 25v blk blk tp8 tp2 red tb1 3 tb1 4 l3 10 h c9 0.1 f tp6 blk + av d d tp10 c8 0.1 f c5 10 f 25v blk blk tp9 tp5 red figure 17. evaluation board: power supply and digital inputs
rev. 0 ad9740 ?16? r6 opt s2 iouta 2 a b jp10 1 3 ix r11 50 c13 10pf jp8 iout s3 4 5 6 3 2 1 t1 t1-1t jp9 c12 10pf r10 50 s1 ioutb 1 2 3 ab jp11 iy 1 ext 2 3 int ab jp5 ref + + c14 10 f 16v c16 0.1 f c17 0.1 f av d d dvdd ckext db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 av d d c15 10 f 16v c18 0.1 f c19 0.1 f cut under dut jp6 jp4 r5 10k dvdd r4 50 clock s5 clock tp1 wht dvdd av d d dvdd r2 10k jp2 mode tp3 wht ref c2 0.1 f c1 0.1 f c11 0.1 f r1 2k 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 u1 ad9740 sleep tp11 wht r3 10k clock dvdd dcom mode av d d reserved iouta ioutb a com nc fs adj refio reflo sleep db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 av d d figure 18. evaluation board: output signal conditioning
rev. 0 ad9740 ?17? figure 19. primary side figure 20. secondary side
rev. 0 ad9740 ?18? figure 21. ground plane figure 22. power plane
rev. 0 ad9740 ?19? figure 23. assembly ? primary side figure 24. assembly ? secondary side
rev. 0 ?20? c02911?0?5/02(0) printed in u.s.a. ad9740 outline dimensions dimensions shown in inches and (mm) 28-lead standard small outline package (soic) (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) 45 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 28 15 14 1 28-lead thin shrink so package (tssop) (ru-28) 28 15 14 1 0.386 (9.80) 0.378 (9.60) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0

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